All outputs verified with qiskit 2.5.1 / qiskit-ibm-runtime 0.48.0 / qiskit-aer 0.17.2.

MCQ answers

Q1 — B. circuit.parameters is always sorted alphabetically by name, regardless of insertion order: [Parameter(a), Parameter(b), Parameter(z)].

Q2 — C. List binding follows the sorted order from Q1: a=0.1, b=0.2, z=0.3. The rx gate uses z, so it gets 0.3. Verified draw: Rx(0.3) Ry(0.1) Rz(0.2).

Q3 — C. Dicts may bind a subset (the rest stay symbolic). A list must match num_parameters exactly or you get ValueError: Mismatching number of values and parameters.... bind_parameters was removed in Qiskit 1.0 (D is wrong).

Q4 — A. With inplace=True, assign_parameters mutates qc and returns None. So result is None and qc.num_parameters is 0.

Q5 — B. Standalone parameters use string sort: "t10" < "t2" because '1' < '2', giving [t10, t2]. ParameterVector elements sort numerically by index: [t[2], t[10]]. Verified both.

Q6 — B. 2*a and a + π/2 are two ParameterExpressions built on the same Parameter(a), so num_parameters is 1.

Q7 — B. Substituting a=π/2: rx angle = 2·(π/2) = π; ry angle = π/2 + π/2 = π. Verified: Rx(π) Ry(π).

Q8 — C. if_test takes a single tuple (clbit_or_creg, value) and is used as a context manager. A is removed API (c_if deleted in Qiskit 2.0); B passes two positional args instead of a tuple; D is invented.

Q9 — A. The context manager yields an else-handle: with qc.if_test((c, 1)) as else_: then with else_:. (C's three-argument body form exists but is not "the only" form — A is the canonical builder-style answer.)

Q10 — C. A register condition compares the register's integer value; 3 = binary 11, i.e. both bits are 1.

Q11 — B. Control-flow bodies are stored as a single operation on the outer circuit: OrderedDict({'for_loop': 1}). The three x's live inside the loop body, not in the outer count.

Q12 — B. Verified error: QiskitError: 'StatevectorSampler cannot handle ControlFlowOp'. Use AerSimulator / qiskit_aer.primitives.SamplerV2 for dynamic circuits locally.

Q13 — A. The v2.x builder is with qc.switch(creg) as case: with with case(value): blocks, multiple values per case allowed (case(1, 2)), and case(case.DEFAULT) for fallthrough. Verified: op appears as switch_case.

Q14 — B. V2 primitives require ISA circuits — target basis gates only, all 2-qubit gates on coupled pairs. Non-ISA circuits are rejected by IBM runtime.

Q15 — B. generate_preset_pass_manager(optimization_level=..., backend=...) then pm.run(qc) is the v2.x standard. qiskit.execute was removed; C and D don't exist.

Q16 — C. Default optimization level is 2 in v2.x for both APIs (docstring: "If None, level 2 will be chosen as default"). It was 1 in older Qiskit — classic trap.

Q17 — A. init → layout → routing → translation → optimization → scheduling. Verified: pm.stages == ('init', 'layout', 'routing', 'translation', 'optimization', 'scheduling'). Routing must precede translation in the preset pipeline; D is the decoy.

Q18 — B. Level 0's trivial layout maps virtual 0,1,2 → physical 0,1,2 on the line 0-1-2-3-4; cx(0, 2) is uncoupled, so one SWAP (3 cx) is inserted: 2 + 3 = 5. Level 3's Sabre layout ([3, 2, 4, 0, 1]) needs no SWAP, keeping 2 cx.

Q19 — B. (ii) and (iii) are true. (i) is false: an ISA circuit contains only basis gates (rz, sx, x, cx on Manila) — h is translated away. Verified: transpiled ry(theta) gives {'sx': 2, 'rz': 2} with theta still unbound in an rz, and isa.layout is a TranspileLayout while the input circuit's .layout is None.

Q20 — C. backend.target (a Target) is the v2.x single source of truth: operations, connectivity, errors, durations. configuration()/properties() are legacy V1 accessors.

Lab solutions

Lab A — ParameterVector sweep through a PUB

Verified output (seed=42, shots=1000):

(3,)
{'0': 1000}
{'1': 497, '0': 503}
{'1': 1000}

res.data.c.shape is (3,) — one PUB with 3 parameter sets produces a BitArray with a leading sweep axis of length 3; index it as res.data.c[i].
ry(0)|0⟩ = |0⟩ → all '0'. ry(π)|0⟩ = |1⟩ (up to global phase) → all '1'.
ry(π/2) gives P(0) = cos²(π/4) = 0.5, but 1000 samples of a fair coin fluctuate (σ = √(1000·0.25) ≈ 16), hence 503/497, not exactly 500/500.
Key takeaway: the circuit was never bound — values traveled in the PUB (circuit, sweep).

Lab B — GHZ at level 0 vs level 3

Verified output (deterministic across runs on this backend):

L0: depth=9 ops={'cx': 5, 'measure': 3, 'rz': 2, 'sx': 1, 'barrier': 1}
L3: depth=6 ops={'measure': 3, 'rz': 2, 'cx': 2, 'sx': 1, 'barrier': 1}

isa.layout.initial_index_layout(): level 0 → [0, 1, 2, 3, 4] (trivial); level 3 → [3, 2, 4, 0, 1] (Sabre-chosen).
Level 0: trivial layout leaves cx(0, 2) on uncoupled physical qubits 0 and 2 → routing inserts 1 SWAP = 3 cx → 5 cx total, depth 9.
Level 3: layout places the interacting qubits on adjacent hardware qubits → no SWAP, 2 cx, depth 6. Both circuits still contain exactly h-equivalent rz/sx gates (2 rz + 1 sx) because h is not a Manila basis gate.

Lab C — active reset with `if_test`

Verified output (Aer SamplerV2, seed=7, shots=1000):

{'01': 501, '00': 499}

Bitstring reads c[1] c[0] (clbit 1 leftmost, little-endian).
c[0] records the 50/50 H outcome → right bit splits ≈ 500/500 (...0 vs ...1).
The if_test flips the qubit back to |0⟩ whenever c[0] was 1, so the final measurement into c[1] is always 0 → left bit is '0' in every shot.
'10' and '11' never appear: that would mean the qubit ended in |1⟩, which the conditional reset makes impossible (up to noise on real hardware).