Question Bank

Parameterized circuits, dynamic circuits, transpilation. Qiskit v2.x. No answers here — see solution-bank.md.

Q1. What is printed?

from qiskit import QuantumCircuit
from qiskit.circuit import Parameter
 
b = Parameter("b"); a = Parameter("a"); z = Parameter("z")
qc = QuantumCircuit(1)
qc.rx(z, 0)
qc.ry(a, 0)
qc.rz(b, 0)
print(list(qc.parameters))

• A. [Parameter(z), Parameter(a), Parameter(b)]
• B. [Parameter(a), Parameter(b), Parameter(z)]
• C. [Parameter(b), Parameter(a), Parameter(z)]
• D. A TypeError — three different parameters cannot share a circuit

Q2. Continuing Q1, after bound = qc.assign_parameters([0.1, 0.2, 0.3]), which angle does the rx gate carry?

• A. 0.1
• B. 0.2
• C. 0.3
• D. It is still symbolic; lists only bind ParameterVectors

Q3. Which statement about assign_parameters in Qiskit v2.x is TRUE?

• A. Passing a dict with only some of the circuit's parameters raises an error
• B. Passing a list with fewer values than parameters silently binds the sorted prefix
• C. Partial binding is supported with a dict; a list must cover every parameter
• D. bind_parameters remains available as a faster alias

Q4. What does this print?

from qiskit import QuantumCircuit
from qiskit.circuit import Parameter
 
c = Parameter("c")
qc = QuantumCircuit(1)
qc.rx(c, 0)
result = qc.assign_parameters({c: 0.5}, inplace=True)
print(result, qc.num_parameters)

• A. None 0
• B. A bound QuantumCircuit and 0
• C. None 1
• D. A bound QuantumCircuit and 1

Q5. Two standalone parameters named t2 and t10 are used in a circuit, and separately a ParameterVector("t", 12) circuit uses t[10] and t[2]. How do circuit.parameters order them?

• A. Standalone: [t2, t10]; vector elements: [t[2], t[10]]
• B. Standalone: [t10, t2]; vector elements: [t[2], t[10]]
• C. Standalone: [t10, t2]; vector elements: [t[10], t[2]]
• D. Both orderings are by insertion order

Q6. What is printed?

import numpy as np
from qiskit import QuantumCircuit
from qiskit.circuit import Parameter
 
a = Parameter("a")
qc = QuantumCircuit(1)
qc.rx(2 * a, 0)
qc.ry(a + np.pi / 2, 0)
print(qc.num_parameters)

• A. 0
• B. 1
• C. 2
• D. 3

Q7. Continuing Q6, after qc.assign_parameters({a: np.pi / 2}), the gate angles are:

• A. rx(π/2), ry(π/2)
• B. rx(π), ry(π)
• C. rx(π), ry(π/2)
• D. rx(2a), ry(a + π/2) — expressions cannot be bound through a single parameter

Q8. In Qiskit v2.x, which is the correct way to apply an X gate to qubit 1 only when classical bit 0 equals 1?

• A. qc.x(1).c_if(qc.clbits[0], 1)
• B. with qc.if_test(qc.clbits[0], 1): qc.x(1)
• C. with qc.if_test((qc.clbits[0], 1)): qc.x(1)
• D. qc.if_else(qc.clbits[0] == 1, qc.x, 1)

Q9. Which construct provides an else branch in v2.x?

• A. with qc.if_test((c, 1)) as else_: ... then with else_: ...
• B. with qc.if_test((c, 1)): ... ; with qc.else_test(): ...
• C. qc.if_test((c, 1), true_body, false_body) is the only form supporting else
• D. Dynamic circuits do not support else branches; use two if_tests with values 1 and 0

Q10. A 2-bit ClassicalRegister cr holds measurement results. What does with qc.if_test((cr, 3)): test?

• A. That at least 3 shots measured 1
• B. That clbit 3 of the circuit equals 1
• C. That the register value equals the integer 3, i.e. both bits read 1
• D. Nothing — registers cannot be used in if_test, only single clbits

Q11. What does qc.count_ops() report for this circuit?

from qiskit import QuantumCircuit
qc = QuantumCircuit(1)
with qc.for_loop(range(3)):
    qc.x(0)
print(qc.count_ops())

• A. OrderedDict({'x': 3})
• B. OrderedDict({'for_loop': 1})
• C. OrderedDict({'for_loop': 1, 'x': 3})
• D. OrderedDict({'x': 1})

Q12. A student runs a circuit containing if_test through StatevectorSampler. What happens?

• A. It runs; the conditional branch is averaged over
• B. QiskitError: 'StatevectorSampler cannot handle ControlFlowOp'
• C. It runs only if shots=1
• D. The if_test is silently removed

Q13. Which is a correct v2.x switch statement over a classical register cr?

• A. with qc.switch(cr) as case: with case(0): qc.x(0); with case(case.DEFAULT): qc.h(0)
• B. qc.switch(cr, {0: x_gate, 'default': h_gate})
• C. with qc.switch(cr == 0): qc.x(0)
• D. with qc.case(cr, 0): qc.x(0)

Q14. Why must circuits be transpiled before running on IBM hardware with V2 primitives?

• A. Primitives only accept OpenQASM 2 strings
• B. V2 primitives reject circuits that are not ISA circuits — expressed in the target's basis gates and respecting its coupling map
• C. Hardware supports any gate, but transpiling reduces cost billing
• D. Only circuits with more than 10 qubits require transpilation

Q15. What is the v2.x-preferred code to get an ISA circuit for a backend?

• A. qc_isa = qiskit.execute(qc, backend)
• B. pm = generate_preset_pass_manager(optimization_level=1, backend=backend); qc_isa = pm.run(qc)
• C. qc_isa = backend.transpile(qc, level=1)
• D. qc_isa = qc.to_isa(backend.target)

Q16. If optimization_level is not specified for transpile() or generate_preset_pass_manager() in Qiskit v2.x, which level is used?

• A. 0
• B. 1
• C. 2
• D. 3

Q17. Put the preset pass manager stages in order.

• A. init → layout → routing → translation → optimization → scheduling
• B. init → translation → layout → routing → optimization → scheduling
• C. layout → init → translation → routing → scheduling → optimization
• D. init → layout → translation → routing → optimization → scheduling

Q18. A 3-qubit GHZ (h(0); cx(0,1); cx(0,2); measure_all()) is transpiled for FakeManilaV2 (linear coupling 0-1-2-3-4). Level 0 produces {'cx': 5, ...} while level 3 produces {'cx': 2, ...}. What best explains the extra 3 cx at level 0?

• A. Level 0 decomposes each h into 3 cx
• B. Level 0 uses trivial layout, so cx(0, 2) is uncoupled and routing inserts one SWAP = 3 cx; level 3 finds a SWAP-free layout
• C. Level 0 duplicates gates for error mitigation
• D. Level 3 removes 3 cx by cancelling them against measurements

Q19. After isa = pm.run(qc) on a real/fake backend, which statements are TRUE? (i) isa.count_ops() may contain h (ii) isa.layout is a TranspileLayout while qc.layout is None (iii) unbound parameters can survive transpilation inside basis-gate angles

• A. i and ii
• B. ii and iii
• C. i and iii
• D. all three

Q20. Which object does the v2.x transpiler consume as the single description of a backend's basis gates, connectivity, and instruction properties?

• A. backend.configuration()
• B. backend.properties()
• C. backend.target
• D. backend.coupling_map only

Answers with explanations: solution-bank.md.